Integrated circuits (IC) may be used in a wide range of designs and products, some integrated circuits may include Non Volatile Memory (NVM) arrays. An NVM array may be composed of NVM cells, ancillary circuitry, controller and additional circuits. The ancillary circuitry which may include for example: array controls, address decoding circuits and sense amplifiers (SA). SAs may be configured to determine a value/level of one or more targeted NVM cell.
Some memory array types may include NVM arrays, floating gate arrays, array of eCT cells, array of MirrorBit cells, charge trapping cells and more.
The NVM cells may be single bit or multi-level storage cells and the cells may be programmable to different states, for example in a single bit configuration the cell may be programmable to either an erased (ERS) or programmed (PRG) stage.
According to some embodiments, the NVM cells may be accessed through wordlines (WLs), bitlines (BLs), select lines (SLs), memory gate (MGs) or otherwise. For each operational mode (Programming of cells, Erasing of cells, Reading of cells etc.) the WLs BLs SLs and/or MGs may be activated accordingly. Which WL, which BL, which SL and which MGs as well as if to operate them at all and to what voltage to supply to them is dependent on the mode (read algorithm, program algorithm, read algorithm and so on) and the selected addresses, the specific technology being used and more. Note, that some arrays may not include SLs, MGs or WLs or otherwise.
Some transistor types which may be used in associated circuitry are Pmos, Nmos, low voltage (LV) Nmos, LV Pmos, high voltage (HV) Nmos and HV Pmos, Zmos, BJT and more. HV transistors/cells may be differentiated from LV transistors/cells by being designed/configured to enable operation in a higher range of voltages across their channel compared to LV cells (for example, between a drain node and a source node of the transistor) and/or across the gate (for example: between their gate and bulk or ground node) and may include a thick oxide region compared to LV devices.